Simultaneous V_t selection and assignment for leakage optimization
Khandelwal, V.; Davoodi, A.; Srivastava, A.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Volume 13, Issue 6, June 2005 Page(s): 762 - 765
Digital Object Identifier   10.1109/TVLSI.2005.844304
Summary:This paper presents a novel approach for leakage optimization through simultaneous V_t selection and assignment. V_t selection implies deciding the right value for V_t and assignment implies deciding which gates should be assigned a particular threshold voltage. We also include the effect of variability in threshold voltage on delay and leakage due to fabrication process variations in our formulations and present a scheme that lets the designer control the leakage and delay variability in his design. The proposed algorithm is a general mathematical formulation that has been shown to trivially extend to multiple threshold voltages.

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