Design of ultrahigh-speed low-voltage CMOS CML buffers and latches
Heydari, P.; Mohanavelu, R.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Volume 12, Issue 10, Oct. 2004 Page(s): 1081 - 1093
Digital Object Identifier   10.1109/TVLSI.2004.833663
Summary: A comprehensive study of ultrahigh-speed current-mode logic (CML) buffers along with the design of novel regenerative CML latches will be illustrated. First, a new design procedure to systematically design a chain of tapered CML buffers is proposed. Next, two new high-speed regenerative latch circuits capable of operating at ultrahigh-speed data rates will be introduced. Experimental results show a higher performance for the new latch architectures compared to the conventional CML latch circuit at ultrahigh-frequencies. It is also shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.

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