Timing driven gate duplication
Srivastava, A.; Kastner, R.; Chunhong Chen; Sarrafzadeh, M.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Volume 12, Issue 1, Jan. 2004 Page(s): 42 - 51
Digital Object Identifier 10.1109/TVLSI.2003.820527
Summary: In the past few years, gate duplication has been studied as a strategy for cutset minimization in partitioning problems. This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary inputs(PI) in topologically sorted order evaluating tuples at the input pins of gates. The tuple's first component corresponds to the input pin required time if that gate is not duplicated. The second component corresponds to the input pin required time if that gate were duplicated. After tuple evaluation the algorithm traverses the network from PI to PO in topologically sorted order, deciding the gates to be duplicated. The last and final traversal is again from PO to PI, in which the gates are physically duplicated. Our algorithm uses the dynamic programming structure. We report delay improvements over other optimization methodologies. Gate duplication, along with other optimization strategies, can be used for meeting the stringent delay constraints in today's ultra complex designs.
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