On gate level power optimization using dual-supply voltages
Chunhong Chen; Srivastava, A.; Sarrafzadeh, M.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Volume 9, Issue 5, Oct 2001 Page(s):616 - 629
Digital Object Identifier 10.1109/92.953496
Summary:In this paper, we present an approach for applying two supply
voltages to optimize power in CMOS digital circuits under the timing
constraints. Given a technology-mapped network, we first analyze the
power/delay model and the timing slack distribution in the network. Then
a new strategy is developed for timing-constrained optimization issues
by making full use of stacks. Based on this strategy, the power
reduction is translated into the polynomial-time-solvable
maximal-weighted-independent-set problem on transitive graphs. Since
different supply voltages used in the circuit lead to totally different
power consumption, we propose a fast heuristic approach to predict the
optimum dual-supply voltages by looking at the lower bound of power
consumption in the given circuit. To deal with the possible power
penalty due to the level converters at the interface of different supply
voltages, we use a “constrained F-M” algorithm to minimize
the number of level converters. We have implemented our approach under
an SIS environment. Experiment shows that the resulting lower bound of
power is tight for most circuits and that the predicted
“optimum” supply voltages are exactly or very close to the
best choice of actual ones. The total power saving of up to 26% (average
of about 20%) is achieved without degrading the circuit performance,
compared to the average power improvement of about 7% by the gate sizing
technique based on a standard cell library. Our technique provides the
power-delay tradeoff by specifying different timing constraints in
circuits for power optimization
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