Quantitative study of the impact of design and synthesis options onprocessor core performance
Bautista, T.; Nunez, A.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Volume 9, Issue 3, Jun 2001 Page(s):461 - 473
Digital Object Identifier   10.1109/92.929580
Summary:In this paper, we present experimental results obtained during the modeling, design, and implementation of a full set of versions of SPARC v.8 Integer Unit cores aimed at embedded applications. VHDL is the description language, Synopsys is the tool used for logical synthesis, and Duet Technologies' Epoch for obtaining the physical layout of the final circuits. These are mapped to 0.50- and 0.35-μm, three metal layer processes in order to study the impact of VLSI scaling on SPARC microarchitectural features. The quantitative results obtained characterize suitable points in the design space. They show the extent to which microarchitecture, design, datapath granularity, and megacell decisions affect performance and cost functions. Design space exploration down to physical layouts is made possible by modeling techniques based on configurable VHDL descriptions

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