A 80 Mb/s low-power scalable turbo codec core
Giulietti, A.; Bougard, B.; Derudder, V.; Dupont, S.; Weijers, J.-W.; Van der Perre, L.
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Volume , Issue , 2002 Page(s): 389 - 392
Digital Object Identifier 10.1109/CICC.2002.1012851
Summary:Turbo coding has reached the step in which its astonishing coding gain is already being proven in real applications. Moreover, its applicability to future broadband communications systems is starting to be investigated. In order to be useful in this domain, special turbo codec architectures that cope with low latency, high throughput, low power consumption and high flexibility are needed. This paper presents an implementation of a convolutional turbo codec core based on innovative solutions for those requirements. The combination of a systematic data storage and transfer optimization with high and low level architectural solutions yields a final throughput up to 80.7 Mb/s, a decoding latency of 10 μs and a power consumption of less than 50 nJ/bit. The 14.7 mm2 full-duplex full-parallel core, implemented in a CMOS 0.18 μm technology, is a complete flexible solution for broadband turbo coding.
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