On the complexity of switch programming in fault-tolerantconfigurable chips
Shi, W.; Kumar, K.; Lombardi, F.
Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on
Volume , Issue , 2000 Page(s):125 - 133
Digital Object Identifier 10.1109/DFTVS.2000.887150
Summary:Given a programmable chip (such as a WSI systolic array, or a
field programmable gate array (FPGA)) made of equally-like configurable
logic blocks (cells), the problem of programming the interconnect
resources (consisting of switches) has been well studied in the
literature. This process can be used for fault tolerance by logically
reconfiguring the fault free cells of the array into a new array as well
as to customize the FPGA by configuring it to perform the desired
functions. Once the desired logical configuration has been achieved (as
an the presence of faulty cells), the (programmable) switches in the
interconnect resources of the array must be programmed to implement the
target topology on the physical array. In this paper, we study the
problem of minimizing the programming time (or cost) required for
implementing this step. We show that current techniques are not likely
to lead to cost optimal polynomial time algorithms, because the
underlying covering problems are NPC-complete in the strong sense. The
NPC-completeness is also extended to grid arrays
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