A dynamic voltage scaled microprocessor system
Burd, T.; Pering, T.; Stratakos, A.; Brodersen, R.
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Volume , Issue , 2000 Page(s):294 - 295, 466
Digital Object Identifier 10.1109/ISSCC.2000.839787
Summary:The microprocessor system in portable electronic devices often has
a time-varying computational load which is comprised of: (1)
compute-intensive and low-latency processes, (2) background and
high-latency processes, and (3) system idle. The key design objectives
for the processor systems in these applications are providing the
highest possible peak performance for the compute-intensive code (e.g.,
handwriting recognition, image decompression) while maximizing the
battery life for the remaining low performance periods. If clock
frequency and supply voltage are dynamically varied in response to
computational load demands, then energy consumed per process can be
reduced for the low computational periods, while retaining peak
performance when required. This strategy, which achieves the highest
possible energy efficiency for time-varying computational loads, is
called dynamic voltage scaling (DVS)
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