A 1 V heterogeneous reconfigurable processor IC for basebandwireless applications
Zhang, H.; Prabhu, V.; George, V.; Wan, M.; Benes, M.; Abnous, A.; Rabaey, J.M.
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Volume , Issue , 2000 Page(s):68 - 69, 448
Digital Object Identifier 10.1109/ISSCC.2000.839694
Summary:The Pleiades processor approach combines an on-chip microprocessor
with an array of heterogeneous programmable computational units of
different granularities (called satellite processors) connected by a
reconfigurable interconnect network. The microprocessor supports the
control-intensive components of the applications as well as the
reconfiguration, while repetitive and regular data-intensive loops
(called kernels) are directly mapped on the array of satellites by
configuring the satellite parameters and the interconnections between
them. Synchronization between the satellite processors is by a
data-driven communication protocol in accordance with the data-flow
nature of the computations performed in the kernels. A generalized
interface wrapper is placed around each satellite processor to comply
with the communication protocol. This spatial programming approach
results in energy efficiency levels of 50-100 MIPS/mW, at least an order
of magnitude better than what can be accomplished in comparable DSP
processors, by exploiting the locality of the computations and the
correlations within data streams, and by distributing the control
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