An integrated temporal partitioning and partial reconfigurationtechnique for design latency improvement
Ganesan, S.; Vemuri, R.
Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings
Volume , Issue , 2000 Page(s):320 - 325
Digital Object Identifier 10.1109/DATE.2000.840290
Summary:Partially reconfigurable processors provide the unique ability by
which a part of the device can be reconfigured, while the remaining part
is still operational. In this paper, we present a novel partitioning
methodology that temporally partitions a design for such a partially
reconfigurable processor and improves design latency by minimizing
reconfiguration overhead. This is achieved by overlapping execution of
one temporal partition with the reconfiguration of another, using the
processors partial reconfiguration capability. We have incorporated
block-processing in the partitioning framework for reducing
reconfiguration overhead of partitioned designs. A highlight of our
partitioner is it's ability to handle loops and conditional constructs
in the input specification. The proposed methodology was tested on
several examples on the Xilinx 6200 FPGA. The results show significant
reduction in the design latency, leading to a considerable speed-up due
to partial reconfiguration
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