A capacitorless double-gate DRAM cell
Hu, C.; Tsu-Jae King; Chenming Hu
Electron Device Letters, IEEE
Volume 23, Issue 6, Jun 2002 Page(s):345 - 347
Digital Object Identifier   10.1109/LED.2002.1004230
Summary:A capacitorless double-gate DRAM (DG-DRAM) cell is proposed in this study. Its dual gates and thin body reduce off state leakage and. disturb problems. Dopant fluctuations, which can be particularly important in high-density arrays, are avoided by using a thin, lightly doped body. The cell's large body coefficient ((dV_T)/(dV_BD) transforms small gains of body potential into increased drain current. MEDICI simulations for 85°C show that a DG-DRAM cell may sustain a measurable change in drain current several hundred milliseconds after programming. These characteristics suggest that a thin body, double-gate cell is an interesting candidate for high density DRAM technologies

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