Rationale and challenges for optical interconnects to electronicchips
Miller, D.A.B.
Proceedings of the IEEE
Volume 88, Issue 6, Jun 2000 Page(s):728 - 749
Digital Object Identifier 10.1109/5.867687
Summary:The various arguments for introducing optical interconnections to
silicon CMOS chips are summarized, and the challenges for optical,
optoelectronic, and integration technologies are discussed. Optics could
solve many physical problems of interconnects, including precise clock
distribution, system synchronization (allowing larger synchronous zones,
both on-chip and between chips), bandwidth and density of long
interconnections, and reduction of power dissipation. Optics may relieve
a broad range of design problems, such as crosstalk, voltage isolation,
wave reflection, impedence matching, and pin inductance. It may allow
continued scaling of existing architectures and enable novel highly
interconnected or high-bandwidth architectures. No physical breakthrough
is required to implement dense optical interconnects to silicon chips,
though substantial technological work remains. Cost is a significant
barrier to practical introduction, though revolutionary approaches exist
that might achieve economies of scale. An Appendix analyzes scaling of
on-chop global electrical interconnects, including line inductance and
the skin effect, both of which impose significant additional constraints
on future interconnects
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