A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic residue amplification
Hu, J.; Dolev, N.; Murmann, B.
VLSI Circuits, 2008 IEEE Symposium on
Volume , Issue , 18-20 June 2008 Page(s):216 - 217
Digital Object Identifier   10.1109/VLSIC.2008.4586012
Summary:An ultra-low power pipelined ADC is realized by replacing conventional op-amp circuits with dynamic source-follower gain stages. The presented 90-nm CMOS converter operates at 50 MS/s and achieves an SNDR of 49.4 dB while dissipating 1.44 mW from a 1.2-V supply.

» View citation and abstract

Log in by entering your IEEE Web Account Username and Password.

IEEE Communications Society members: If you subscribe to the IEEE Electronic Periodicals Package or IEEE Electronic Periodicals Package Plus, you must access your subscription at www.comsoc.org.

Check with your librarian, information professional, or system manager to determine if you need to log in. Please complete the online Technical Support Form if you need assistance.

Select the Purchase History link to access the document. You will have 5 Days after purchase to access the Full Text PDF. Please complete the online Technical Support Form if you need assistance.

• Search and access Abstract records free of charge
• Register for table of contents alerts
• Purchase Full Text PDF documents

» Learn more about subscription options or how to become an IEEE Member.