Predictive control algorithm for phase-locked loops
Abusleme, A.; Murmann, B.
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Volume , Issue , 18-21 May 2008 Page(s):1528 - 1531
Digital Object Identifier   10.1109/ISCAS.2008.4541721
Summary:Phase-locked loops (PLLs) exhibit a tradeoff between settling time and noise rejection, due to the fact that a low noise PLL requires a narrow bandwidth (BW) loop filter, which degrades settling time. However, the moments when fast settling or good noise rejection is required are clearly identified in a PLL, and this can be used to overcome this tradeoff. A recent technique - PLL gear shifting - exploits this fact by modifying the loop filter BW according to the PLL current objective. In this work, a similar solution based on predictive control techniques is presented. Through a very simple digital loop filter an optimal response is obtained, where a single parameter controls the bandwidth to improve either settling time or noise rejection.

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