Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits
Orshansky, M.; Milor, L.; Pinhong Chen; Keutzer, K.; Chenming Hu
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Volume 21, Issue 5, May 2002 Page(s):544 - 553
Digital Object Identifier 10.1109/43.998626
Summary:In this paper we address both empirically and theoretically the
impact of an advanced manufacturing phenomenon on the performance of
high-speed digital circuits. Using data collected from an actual
state-of-the-art fabrication facility, we conducted a comprehensive
characterization of an advanced 0.18-μm CMOS process. The measured
data revealed a significant systematic, rather than random spatial
intrachip variability of MOS gate length, leading to large circuit path
delay variation. The delay of the critical path of a combinational logic
block varies by as much as 17%, and the global skew is increased by 8%.
Thus, a significant timing error and performance loss takes place if
variability is not properly addressed. We derive a model, which allows
estimating performance degradation for the given circuit and process
parameters. We demonstrate explicitly that intrachip Lgate variation has
a significant detrimental impact on the overall circuit performance,
shifting the entire distribution of clock frequencies toward slower
values. This is in striking contrast to the impact of interchip Lgate
variation, traditionally considered in statistical circuit analysis,
which leads to the variation of chip clock frequencies around the
average value. Moreover, analysis shows that the spatial, rather than
proximity-dependent systematic Lgate variability, is the main cause of
large circuit speed degradation. The degradation is worse for the
circuits with a larger number of critical paths and shorter average
logic depth. We propose a location-dependent timing analysis methodology
that allows mitigation of the detrimental effects of Lgate variability
and have developed a tool linking the layout-dependent spatial
information to circuit analysis. We discuss the details of practical
implementation of the methodology, and provide guidelines for managing
design complexity
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