A Realization Algorithm Using Three-Input Majority Elements
Riseman, Edward M.
Electronic Computers, IEEE Transactions on
Volume EC-16, Issue 4, Aug. 1967 Page(s):456 - 462
Digital Object Identifier   10.1109/PGEC.1967.264649
Summary:A modification of Akers' method of realizing Boolean functions with three-input majority gates is presented. One of the fundamental parts in Akers' procedure is the construction of a logically passive self-dual, or LPSD. This paper presents a more precise construction of the LPSD. In addition, a procedure is described to adapt the method to minimization of the number of delay elements. A delay element table is introduced to aid in the selection of majority gates. A second factor in reducing delay elements is limiting the number of levels of logic in the realization. Examples illustrate the substantial reduction in delay elements when these methods are employed.

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