Bilateral Testing of Nano-scale Fault-tolerant Circuits
Lei Fang; Michael S. Hsiao
Defect and Fault Tolerance in VLSI Systems, 2006. DFT apos;06. 21st IEEE International Symposium on
Volume , Issue , Oct. 2006 Page(s):309 - 317
Digital Object Identifier 10.1109/DFT.2006.17
Summary:As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. Because fault-tolerant hardwares help to mask the effects caused by increased levels of defects, testing the functionality of the chip together with the embedded fault-tolerance becomes a tremendous challenge. In this paper, a new bilateral testing framework for nano circuits is proposed, where multiple stuck-at faults across different modules in a triple module redundancy (TMR) architecture are considered. In addition, a new test generator is presented for the bilateral testing that takes into account the enormous number of bilateral stuck-at faults possible with new types of guidance in the search, and it can generate a set of vectors that can test the TMR-based nano circuit as a single entity. Experimental results reported for ISCAS'85 and ITC99 circuits demonstrate that the bilateral testing can help to capture many more defects which the single stuck-at fault misses
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