Performance evaluation of the Cray X1 distributed shared-memory architecture
Dunigan, T.H., Jr.; Vetter, J.S.; White, J.B., III; Worley, P.H.
Micro, IEEE
Volume 25, Issue 1, Jan.-Feb. 2005 Page(s): 30 - 40
Digital Object Identifier   10.1109/MM.2005.20
Summary: The Cray X1 supercomputer, introduced in 2002, has several interesting architectural features. Two key features are the X1's distributed shared memory and its vector multiprocessors. The Cray X1 supercomputer's distributed shared memory presents a 64-bit global address space that is directly addressable from every MSP with an interconnect bandwidth per computation rate of 1 byte/flop. In this article, we characterize the performance of the X1's distributed shared-memory system and its interconnection network using microbench-marks and applications.

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