An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators
Ting Wu; Mayaram, K.; Un-Ku Moon
Solid-State Circuits, IEEE Journal of
Volume 42, Issue 4, April 2007 Page(s):775 - 783
Digital Object Identifier   10.1109/JSSC.2007.892194
Summary:A technique for reducing the supply voltage sensitivity of a ring oscillator using on-chip calibration is described. A 1-V 0.13-mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 0.5 to 2 GHz. In the presence of a 10-mV 1-MHz VCO supply noise, the measured rms jitter of the proposed PLL with on-chip calibration is 3.95 ps at a 1.4-GHz operating frequency, while a conventional design measures 8.22 ps rms jitter. For 10-MHz VCO supply noise, the measured rms jitter is improved from 16.8 ps to 3.97 ps. The total power consumption of the PLL is 9.6 mW at 1.4 GHz, and the combined core die area of the PLL and the calibration circuitry is 0.064 mm²

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