A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling
Iroaga, E.; Murmann, B.
Solid-State Circuits, IEEE Journal of
Volume 42, Issue 4, April 2007 Page(s):748 - 756
Digital Object Identifier   10.1109/JSSC.2007.892154
Summary:The residue amplifiers in high-speed pipelined analog-to-digital converters (ADCs) typically determine the converter's overall speed and power performance. We propose a mixed-signal technique that exploits incomplete settling to achieve low power residue amplification. In the first stage of a 12-bit, 75-MS/s proof-of-concept prototype, the employed open-loop residue amplifier dissipates only 2.9 mW from a 3-V supply, achieving >60% amplifier power reduction over a previously reported open-loop residue amplifier implementation and achieving >90% amplifier power reduction over a conventional opamp implementation. Test results show that the converter's maximum signal-to-noise-and-distortion ratio (SNDR) is 65.6 dB. The measured integral and differential nonlinearity are 0.95 LSB and 0.64 LSB, respectively. The experimental chip occupies 7.9 mm² and consumes 273 mW in a 0.35-mum double-poly, quadruple-metal CMOS process

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