A +78 dBm IIP2 CMOS direct downconversion mixer for fully integrated UMTS receivers
Brandolini, M.; Rossi, P.; Sanzogni, D.; Svelto, F.
Solid-State Circuits, IEEE Journal of
Volume 41, Issue 3, March 2006 Page(s): 552 - 559
Digital Object Identifier 10.1109/JSSC.2005.864123
Summary:The demanding dynamic range required by receivers for cell-phone applications makes the design of low-power fully integrated CMOS solutions extremely challenging. Commercially available third-generation (3G) products adopt a hybrid direct conversion architecture, where an inter-stage surface acoustic wave (SAW) filter between low noise amplifier (LNA) and mixer attenuates out-of-band interferers, alleviating linearity requirements set on the downconversion mixer. As a drawback, an off-chip component and an additional LNA are introduced, raising costs. Leveraging an in-depth analysis of second-order inter-modulation mechanisms in active downconversion mixers, this paper presents the design of a 0.18-μm CMOS solution with outstanding linearity and noise performances. The input transconductor is RC degenerated, the output resistors are carefully matched and, most important, the parasitic capacitors at switching pair common sources are tuned out. Sixty samples from two distinct fabrication lots have been characterized. Minimum IIP2 is +78 dBm. For comparison, a second solution where inter-modulation products generated by the switching pair are not filtered out has been fabricated and tested. IIP2 values are always lower. Other measured performance results are: 16-dB gain with 4.5-MHz output bandwidth; +10-dBm out-of-band IIP3; 4-nV/√Hz input referred noise voltage density while drawing 4 mA from 1.8 V.
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