Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor
Pham, D.C.; Aipperspach, T.; Boerstler, D.; Bolliger, M.; Chaudhry, R.; Cox, D.; Harvey, P.; Harvey, P.M.; Hofstee, H.P.; Johns, C.; Kahle, J.; Kameyama, A.; Keaty, J.; Masubuchi, Y.; Pham, M.; Pille, J.; Posluszny, S.; Riley, M.; Stasiak, D.L.; Suzuoki, M.; Takahashi, O.; Warnock, J.; Weitzel, S.; Wendel, D.; Yazawa, K.
Solid-State Circuits, IEEE Journal of
Volume 41, Issue 1, Jan. 2006 Page(s): 179 - 196
Digital Object Identifier 10.1109/JSSC.2005.859896
Summary: This paper reviews the design challenges that current and future processors must face, with stringent power limits, high-frequency targets, and the continuing system integration trends. This paper then describes the architecture, circuit design, and physical implementation of a first-generation Cell processor and the design techniques used to overcome the above challenges. A Cell processor consists of a 64-bit Power Architecture processor coupled with multiple synergistic processors, a flexible IO interface, and a memory interface controller that supports multiple operating systems including Linux. This multi-core SoC, implemented in 90-nm SOI technology, achieved a high clock rate by maximizing custom circuit design while maintaining reasonable complexity through design modularity and reuse.
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