The microarchitecture of the synergistic processor for a cell processor
Flachs, B.; Asano, S.; Dhong, S.H.; Hofstee, H.P.; Gervais, G.; Roy Kim; Le, T.; Peichun Liu; Leenstra, J.; Liberty, J.; Michael, B.; Hwa-Joon Oh; Mueller, S.M.; Takahashi, O.; Hatakeyama, A.; Watanabe, Y.; Yano, N.; Brokenshire, D.A.; Peyravian, M.; Vandung To; Iwata, E.
Solid-State Circuits, IEEE Journal of
Volume 41, Issue 1, Jan. 2006 Page(s): 63 - 70
Digital Object Identifier   10.1109/JSSC.2005.859332
Summary: This paper describes an 11 FO4 streaming data processor in the IBM 90-nm SOI-low-k process. The dual-issue, four-way SIMD processor emphasizes achievable performance per area and power. Software controls most aspects of data movement and instruction flow to improve memory system performance and core performance density. The design minimizes instruction latency while providing for fine grain clock control to reduce power.

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