A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS
Dorrer, L.; Kuttner, F.; Greco, P.; Torta, P.; Hartig, T.
Solid-State Circuits, IEEE Journal of
Volume 40, Issue 12, Dec. 2005 Page(s): 2416 - 2427
Digital Object Identifier   10.1109/JSSC.2005.856282
Summary:A third-order continuous-time multibit (4 bit) ΔΣ ADC for wireless applications is implemented in a 0.13-μm CMOS process. It is shown that the power consumption can be considerably reduced by using a tracking ADC composed of three comparators with interpolation instead of using a 4-bit flash quantizer. Moreover, the usage of a tracking ADC opens the door to a new forward-looking dynamic element matching (DEM) technique, which helps to reduce the loop delay time and consequently improves the loop stability. The SNR is 74 dB over a bandwidth of 2 MHz. The ADC consumes 3 mW from a 1.5-V supply when clocked at 104 MHz. The active area is 0.3 mm².

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