High-frequency CML clock dividers in 0.13-μm CMOS operating up to 38 GHz
Singh, U.; Green, M.M.
Solid-State Circuits, IEEE Journal of
Volume 40, Issue 8, Aug. 2005 Page(s): 1658 - 1661
Digital Object Identifier   10.1109/JSSC.2005.852420
Summary:The analysis and design of two novel high-speed CMOS clock dividers is discussed. The realizations of these circuits in a 0.13-μm CMOS process show a significant improvement in high-frequency operation compared to a conventional D flip-flop-based divider. Measured sensitivity curves of these dividers give maximum frequency of operation ranging from 20 to 38 GHz with power consumption of 12 mW from a 1.8-V supply voltage.

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