A shared-well dual-supply-voltage 64-bit ALU
Shimazaki, Y.; Zlatanovici, R.; Nikolic, B.
Solid-State Circuits, IEEE Journal of
Volume 39, Issue 3, March 2004 Page(s): 494 - 500
Digital Object Identifier   10.1109/JSSC.2003.822775
Summary:A shared n-well layout technique is developed for the design of dual-supply-voltage logic blocks. It is demonstrated on a design of a 64-bit arithmetic logic unit (ALU) module in domino logic. The second supply voltage is used to lower the power of noncritical paths in the sparse, radix-4 64-bit carry-lookahead adder and in the loopback bus. A 3 mm² test chip in 0.18-μm 1.8-V five-metal with local interconnect CMOS technology that contains six ALUs and test circuitry operates at 1.16 GHz at the nominal supply. For target delay increase of 2.8% energy savings are 25.3% using dual supplies, while for 8.3% increase in delay, 33.3% can be saved.

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