All-MOS charge-redistribution analog-to-digital conversion techniques. II
Suarez, R.E.; Gray, P.R.; Hodges, D.A.
Solid-State Circuits, IEEE Journal of
Volume 10, Issue 6, Dec 1975 Page(s): 379 - 385
Digital Object Identifier  
Summary:For pt.I see ibid., vol.SC-10, no.6, p.371-9 (1975). Describes techniques for performing A/D conversion compatibly with standard single-channel MOS technology. This second paper describes a two-capacitor successive approximation technique which, in contrast to the first, requires considerably less die area, is inherently monotonic in the presence of capacitor ratio errors, and which operates at somewhat lower conversion rate. Factors affecting accuracy and conversion rate are considered analytically. Experimental results from a monolithic prototype are presented; a resolution of eight bits was achieved with an A/D conversion time of 100 μs. Used as a D/A convertor, a settling time of 12.5 μs was achieved. The estimated total die size for a completely monolithic version including logic is 5000 mil/SUP 2/.

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