A fourth-order bandpass Δ-Σ modulator usingsecond-order bandpass noise-shaping dynamic element matching
Ueno, T.; Yasuda, A.; Yamaji, T.; Itakura, T.
Solid-State Circuits, IEEE Journal of
Volume 37, Issue 7, Jul 2002 Page(s):809 - 816
Digital Object Identifier 10.1109/JSSC.2002.1015677
Summary:This paper describes a multibit bandpass ΔΣ modulator
(DSM) for a frequency-interleaved analog-to-digital (A/D) converter
(ADC). A frequency-interleaved ADC using low oversampling ratio (OSR)
DSMs is an attractive approach for broadband and high resolution A/D
conversion. A multibit DSM is suitable for low-oversampling operation;
however, the overall resolution of a multibit DSM is restricted by the
accuracy of the internal D/A converter (DAC). Some methods have been
reported for improving the internal DAC accuracy of a low-pass DSM, but
no bandpass-shaping technique applicable to a bandpass DSM has been
implemented, although some methods have been proposed by using
simulation. This paper proposes a multibit bandpass DSM with bandpass
noise-shaping dynamic element matching (BPNSDEM), which enables bandpass
shaping to mismatch error of the internal DAC, and presents its
implementation. The modulator was implemented in a 0.25-μm CMOS
technology. It operates at a 2.5-V power supply and achieves a
signal-to-noise ratio of 77.4 dB over a 250-kHz bandwidth centered at
566 kHz
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