Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design andscaling trends
Mathew, S.K.; Krishnamurthy, R.K.; Anders, M.A.; Rios, R.; Mistry, K.R.; Soumyanath, K.
Solid-State Circuits, IEEE Journal of
Volume 36, Issue 11, Nov 2001 Page(s):1636 - 1646
Digital Object Identifier 10.1109/4.962283
Summary:In this paper, we present: 1) design of a single-rail
energy-efficient 64-b Han-Carlson ALU, operating at 482 ps in 1.5 V,
0.18-μm bulk CMOS; 2) direct port of this ALU to 0.18-μm partially
depleted SOI process; 3) SOI-optimal redesign of the ALU using a novel
deep-stack quaternary-tree architecture; 4) margining for max-delay
pushout due to reverse body bias in SOI designs; and 5) performance
scaling trends of the ALU designs in 0.13-μm generation. We show that
a direct port of the Han-Carlson ALU to 0.18-μm SOI offers 14%
performance improvement after margining. A redesign of the ALU, using an
SOI-favored deep-stack architecture improves the margined speedup to
19%. A 10% margin was required for the SOI designs, to account for
reverse body-bias-induced max-delay pushout. Preconditioning the
intermediate stack nodes in the dynamic ALU designs reduced this margin
to 2%. Scaling the ALUs to 0.13-μm generation reduces the overall SOI
speedup for both architectures to 9% and 16%, respectively, confirming
the trend that speedup offered by SOI technology decreases with scaling
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