A 0.18-μm CMOS IA-32 processor with a 4-GHz integer executionunit
Hinton, G.; Upton, M.; Sager, D.J.; Boggs, D.; Carmean, D.M.; Roussel, P.; Chappell, T.I.; Fletcher, T.D.; Milshtein, M.S.; Sprague, M.; Samaan, S.; Murray, R.
Solid-State Circuits, IEEE Journal of
Volume 36, Issue 11, Nov 2001 Page(s):1617 - 1627
Digital Object Identifier   10.1109/4.962281
Summary:This paper describes the main features and functions of the Pentium(R) 4 processor microarchitecture. We present the front-end of the machine, including its new form of instruction cache called the trace cache, and describe the out-of-order execution engine, including a low latency double-pumped arithmetic logic unit (ALU) that runs at 4 GHz. We also discuss the memory subsystem, including the low-latency Level 1 data cache that is accessed in two clock cycles. We then describe some of the key features that contribute to the Pentium(R) 4 processor's floating-point and multimedia performance. We provide some key performance numbers for this processor, comparing it to the Pentium(R) III processor

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