Programmable spatial processing imager chip
Gruev, V.; Etienne-Cummings, R.
Electronics Letters
Volume 37, Issue 11, 24 May 2001 Page(s):688 - 690
Digital Object Identifier   10.1049/el:20010455
Summary:The authors present an architectural overview and results from an image processor chip for realising steerable spatial filtering at the focal plane. Convolutions of the image with multiple programmable kernels are realised with area-efficient, real-time circuits. In addition to the raw intensity image, the chip outputs four processed images in parallel. The convolutions are implemented with digitally programmable analogue processors. The chip performs 5.7 GOPS/mW while outputting four processed images in parallel

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