RISC and ASIC-the technologies of the nineties
Holzmann, D.J.; Mayer, U.
CompEuro apos;89., apos;VLSI and Computer Peripherals. VLSI and Microelectronic Applications in Intelligent Peripherals and their Interconnection Networksapos;, Proceedings.
Volume , Issue , 8-12 May 1989 Page(s):5/148 - 5/150
Digital Object Identifier 10.1109/CMPEUR.1989.93505
Summary:The authors discuss the implementation of a
reduced-instruction-set computing (RISC) microprocessor architecture in
a fully integrated complex system solution. In benchmark studies, the
RISC 32-b architecture offers higher performance than conventional 32-b
microprocessors. This higher processing power is achieved by
streamlining the instruction set to the most important and regularly
used instructions, in an architecture which executes these instructions
in one machine cycle while at the same time using a pipeline structure.
RISC microprocessors are implemented typically in high-performance
computers, workstations, and embedded-control real-time systems. The
next generation of system implementation will combine RISC
microprocessors and application-specific IC (ASIC) technology on one
chip for easy transition to newer technologies as they arrive
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