Impact of Scaling on Analog Performance and Associated Modeling Needs
Murmann, B.; Nikaeen, P.; Connelly, D.J.; Dutton, R.W.
Electron Devices, IEEE Transactions on
Volume 53, Issue 9, Sept. 2006 Page(s):2160 - 2167
Digital Object Identifier   10.1109/TED.2006.880372
Summary:This paper explores modeling and technology-scaling issues related to analog performance in advanced CMOS technologies. Performance metrics for analog circuits are defined, to provide insight into the impact of device scaling on power-constrained analog circuit design. Current and previous generation technologies (90 nm and older) are evaluated using standard compact models. Technology nodes below 90 nm are simulated at the device level to show trends in analog performance metrics and to evaluate the impact of nonminimum gate length and alternate doping profiles. Results indicate that the modeling of moderate-to-weak inversion behavior will continue to grow in importance. Simulations suggest that using nonminimum length and drain-side engineered devices at the 45-nm technology node offers an attractive degree of freedom for analog circuit design

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