A spacer patterning technology for nanoscale CMOS
Yang-Kyu Choi; Tsu-Jae King; Chenming Hu
Electron Devices, IEEE Transactions on
Volume 49, Issue 3, Mar 2002 Page(s):436 - 441
Digital Object Identifier   10.1109/16.987114
Summary:A spacer patterning technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-7 nm structures with conventional dry etching. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields critical dimension (CD) variations of minimum-sized features much smaller than that achieved by optical or e-beam lithography. In addition, it also provides a doubling of device density for a given lithography pitch. This method is used to pattern silicon fins for double-gate metal-oxide semiconductor field effect transistors (MOSFETs) (FinFETs) and gate electrode structures for ultrathin body MOSFETs. Process details are presented

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