1/f noise in CMOS transistors for analog applications
Nemirovsky, Y.; Brouk, I.; Jakobson, C.G.
Electron Devices, IEEE Transactions on
Volume 48, Issue 5, May 2001 Page(s):921 - 927
Digital Object Identifier 10.1109/16.918240
Summary:Noise measurements of the 1/f noise in PMOS and NMOS transistors
for analog applications are reported under wide bias conditions ranging
from subthreshold to saturation. Two “low noise” CMOS
processes of 2 μm and 0.5 μm technologies are compared and it is
found that the more advanced process, with 0.5 μm technology,
exhibits significantly reduced 1/f noise, due to optimized processing.
The input referred noise and the power spectral density (PSD) of the
drain current 1/f noise are modeled in saturation as well as in
subthreshold and are compared with the common empirical approaches such
as the SPICE models. The results of this study are useful to the design
and modeling of 1/f noise of CMOS analog circuits
View citation and abstract |
Cart
