FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Hisamoto, D.; Wen-Chin Lee; Kedzierski, J.; Takeuchi, H.; Asano, K.; Kuo, C.; Anderson, E.; Tsu-Jae King; Bokor, J.; Chenming Hu
Electron Devices, IEEE Transactions on
Volume 47, Issue 12, Dec 2000 Page(s): 2320 - 2325
Digital Object Identifier   10.1109/16.887014
Summary:MOSFETs with gate length down to 17 nm are reported. To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed. By using boron-doped Si_0.4Ge_0.6 as a gate material, the desired threshold voltage was achieved for the ultrathin body device. The quasiplanar nature of this new variant of the vertical double-gate MOSFETs can be fabricated relatively easily using the conventional planar MOSFET process technologies.

» View citation and abstract

Log in by entering your IEEE Web Account Username and Password.

IEEE Communications Society members: If you subscribe to the IEEE Electronic Periodicals Package or IEEE Electronic Periodicals Package Plus, you must access your subscription at www.comsoc.org.

Check with your librarian, information professional, or system manager to determine if you need to log in. Please complete the online Technical Support Form if you need assistance.

Select the Purchase History link to access the document. You will have 5 Days after purchase to access the Full Text PDF. Please complete the online Technical Support Form if you need assistance.

• Search and access Abstract records free of charge
• Register for table of contents alerts
• Purchase Full Text PDF documents

» Learn more about subscription options or how to become an IEEE Member.