A 12b, 75MS/s Pipelined ADC Using Incomplete Settling
Iroaga, E.; Murmann, B.
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Volume , Issue , 0-0 0 Page(s):222 - 223
Digital Object Identifier   10.1109/VLSIC.2006.1705390
Summary:This paper proposes a mixed-signal technique that exploits incomplete settling to achieve ultra low power residue amplification. In the first stage of the presented 12-bit, 75-MS/s prototype ADC, the employed open-loop gain stage dissipates only 2.9mW from a 3V supply, achieving a 94% power reduction over a typical op-amp implementation. The complete pipelined ADC achieves a measured SNR of 66dB (f_in = 1MHz), consumes 273mW and occupies 7.9mm in 0.35mum CMOS

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