Optimizing Compiler for the CELL Processor
Eichenberger, A.E.; Oapos;Brien, K.; Peng Wu; Tong Chen; Oden, P.H.; Prener, D.A.; Shepherd, J.C.; Byoungro So; Sura, Z.; Wang, A.; Tao Zhang; Peng Zhao; Gschwind, M.
Parallel Architectures and Compilation Techniques, 2005. PACT 2005. 14th International Conference on
Volume , Issue , 17-21 Sept. 2005 Page(s): 161 - 172
Digital Object Identifier 10.1109/PACT.2005.33
Summary: Developed for multimedia and game applications, as well as other numerically intensive workloads, the CELL processor provides support both for highly parallel codes, which have high computation and memory requirements, and for scalar codes, which require fast response time and a full-featured programming environment. This first generation CELL processor implements on a single chip a Power Architecture processor with two levels of cache, and eight attached streaming processors with their own local memories and globally coherent DMA engines. In addition to processor-level parallelism, each processing element has a Single Instruction Multiple Data (SIMD) unit that can process from 2 double precision floating points up to 16 bytes per instruction. This paper describes, in the context of a research prototype, several compiler techniques that aim at automatically generating high quality codes over a wide range of heterogeneous parallelism available on the CELL processor. Techniques include compiler-supported branch prediction, compiler-assisted instruction fetch, generation of scalar codes on SIMD units, automatic generation of SIMD codes, and data and code partitioning across the multiple processor elements in the system. Results indicate that significant speedup can be achieved with a high level of support from the compiler.
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