Layout generation algorithm for CMOS analog IC cells
Tsien Liang; Syrzycki, M.
Electrical and Computer Engineering, 1998. IEEE Canadian Conference on
Volume 2, Issue , 24-28 May 1998 Page(s):653 - 656 vol.2
Digital Object Identifier   10.1109/CCECE.1998.685581
Summary:This paper presents the development of an algorithm for the placement of transistors in analog IC layout design. The properties and implementation techniques of the algorithm are introduced along with sample layouts produced for a test circuit

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