The MIT Alewife Machine
Agarwal, A.; Bianchini, R.; Chaiken, D.; Chong, F.T.; Johnson, K.L.; Kranz, D.; Kubiatowicz, J.D.; Beng-Hong Lim; Mackenzie, K.; Yeung, D.
Proceedings of the IEEE
Volume 87, Issue 3, Mar 1999 Page(s):430 - 444
Digital Object Identifier 10.1109/5.747864
Summary:A variety of models for parallel architectures, such as shared
memory, message passing, and data flow, have converged in the recent
past to a hybrid architecture form called distributed shared memory
(DSM). Alewife, an early prototype of such DSM architectures, uses
hybrid software and hardware mechanisms to support coherent shared
memory, efficient user level messaging, fine grain synchronization, and
latency tolerance. Alewife supports up to 512 processing nodes connected
over a scalable and cost effective mesh network at a constant cost per
node. Four mechanisms combine to achieve Alewife's goals of scalability
and programmability: software extended coherent shared memory provides a
global, linear address space; integrated message passing allows compiler
and operating system designers to provide efficient communication and
synchronization; support for fine grain computation allows many
processors to cooperate on small problem sizes; and latency tolerance
mechanisms-including block multithreading and prefetching-mask
unavoidable delays due to communication. Extensive results from
microbenchmarks, together with over a dozen complete applications
running on a 32-node prototype, demonstrate that integrating message
passing with shared memory enables a cost efficient solution to the
cache coherence problem and provides a rich set of programming
primitives. Our results further show that messaging and shared memory
operations are both important because each helps the programmer to
achieve the best performance for various machine configurations
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