Techniques for minimizing power dissipation in scan andcombinational circuits during test application
Dabholkar, V.; Chakravarty, S.; Pomeranz, I.; Reddy, S.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Volume 17, Issue 12, Dec 1998 Page(s):1325 - 1333
Digital Object Identifier 10.1109/43.736572
Summary:Reduction of power dissipation during test application is studied
for scan designs and for combinational circuits tested using built-in
self-test (BIST). The problems are shown to be intractable. Heuristics
to solve these problems are discussed. We show that heuristics with good
performance bounds can be derived for combinational circuits tested
using BIST. Experimental results show that considerable reduction in
power dissipation can be obtained using the proposed techniques
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