High-current failure model for VLSI interconnects under short-pulsestress conditions
Banerjee, K.; Amerasekera, A.; Cheung, N.; Chenming Hu
Electron Device Letters, IEEE
Volume 18, Issue 9, Sep 1997 Page(s):405 - 407
Digital Object Identifier   10.1109/55.622511
Summary:Short-time high joule heating causing thermal breakdown of metal interconnects in ESD/EOS protection circuits and I/O buffers has become a reliability concern. Such failures occur frequently during testing for latchup robustness and during ESD/EOS type events. In this work, heating and failure of passivated TiN/AlCu/TiN integrated circuit interconnects in a quadruple level metallization system of a sub-0.5 μm CMOS technology has been characterized under high-current pulse conditions. A model incorporating the heating of the layered metal system and the oxide surrounding it has been developed which relates the maximum allowable current density to the pulse width. The model is shown to be in excellent agreement with experimental results and is applied to generate design guidelines for ESD/EOS and I/O buffer interconnects

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