Area-efficient parallel FIR digital filter implementations
Parker, D.A.; Parhi, K.K.
Application Specific Systems, Architectures and Processors, 1996. ASAP 96. Proceedings of International Conference on
Volume , Issue , 19-21 Aug 1996 Page(s):93 - 111
Digital Object Identifier 10.1109/ASAP.1996.542805
Summary:This paper presents a novel approach for implementing
area-efficient parallel (block) finite impulse response (FIR) filters
that require less hardware than traditional block FIR filter
implementations. Parallel processing is a powerful technique because it
can be used to increase the throughput of a FIR filter or reduce the
power consumption of a FIR filter. However, a traditional block filter
implementation causes a linear increase in the hardware cost (area) by a
factor of L, the block size. In many design situations, this large
hardware penalty cannot be tolerated. Therefore, it is advantageous to
produce parallel FIR filter implementations that require less area than
traditional block FIR filtering structures. In this paper, we propose a
method to design parallel FIR filter structures that require a
less-than-linear increase in the hardware cost. A novel adjacent
coefficient sharing based sub-structure sharing technique is introduced
and used to reduce the hardware cost of parallel FIR filters. A novel
coefficient quantization technique, referred to as a maximum absolute
difference (MAD) quantization process, is introduced and used to produce
quantized filters with good spectrum characteristics. By using a
combination of fast FIR filtering algorithms, a novel coefficient
quantization process and area reduction techniques, we show that
parallel FIR filtering structures with up to a 45% reduction in hardware
is achieved for the given examples
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