Large area defect-tolerant tree architectures
Shi, W.; Fuchs, W.K.
Wafer Scale Integration, 1991. Proceedings., [3rd] International Conference on
Volume , Issue , 29-31 Jan 1991 Page(s):127 - 133
Digital Object Identifier   10.1109/ICWSI.1991.151706
Summary:The authors study the problem of designing large-area defect-tolerant tree architectures under the fault model that each processor, switch, and wire may be defective with independent constant probability. Using expander graphs, it is shown that, for any given constant 0<h<1, there is a design of n processors with layout area O(n) such that the harvest rate is asymptotically h, provided the yield of each switch and wire is above a constant threshold depending on h but independent of n. The significance of this result is that, under this fault model, all previous defect-tolerant tree architectures have a harvest rate that is asymptotically 0

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