Simulating digital circuits with one bit per wire
Appel, A.W.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Volume 7, Issue 9, Sep 1988 Page(s):987 - 993
Digital Object Identifier 10.1109/43.7796
Summary:An algorithm to simulate synchronous digital logic circuits in
space proportional to one bit per wire, as long as the specification has
a hierarchical nature, is described. An entire simulation might fit in
the fast cache of some computers. The simulation algorithm is simple to
implement, and runs relatively quickly. Although the algorithm has a
quadratic worst-case running time, empirical results show that the
running time for typical circuits is close to linear. The algorithm is
reasonably time-efficient in absolute terms (a few microseconds per
gate), although somewhat slower than recently developed event-driven or
straight-line simulators, and much slower than word-parallel
straight-line compiled simulators. In effect, the algorithm produces
behavioral simulators automatically from a circuit description: each
module is a subroutine that may be invoked from other parts of the
circuit
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