OPASYN: a compiler for CMOS operational amplifiers
Koh, H.Y.; Sequin, C.H.; Gray, P.R.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Volume 9, Issue 2, Feb 1990 Page(s):113 - 125
Digital Object Identifier   10.1109/43.46777
Summary:A silicon compilation system for CMOS operational amplifiers (OPASYN) is discussed. The synthesis system takes as inputs system-level specifications, fabrication-dependent technology parameters, and geometric layout rules. It produces a design-rule-correct compact layout of an optimized operational amplifier. The synthesis proceeds in three stages: (1) heuristic selection of a suitable circuit topology; (2) parametric circuit optimization based on analytic models; and (3) mask geometry construction using a macro cell layout style. The synthesis process is fast enough for the program to be used interactively at the system design level by system designers who are inexperienced in operational amplifier design

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