Circuit reliability simulator for interconnect, via, and contactelectromigration
Liew, B.-K.; Fang, P.; Cheung, N.W.; Hu, C.
Electron Devices, IEEE Transactions on
Volume 39, Issue 11, Nov 1992 Page(s):2472 - 2479
Digital Object Identifier   10.1109/16.163460
Summary:A model for predicting Al interconnect and intermetallic contact/via electromigration time-to-failure under arbitrary current waveform is incorporated in a circuit electromigration reliability simulator. The simulator can (1) generate layout advisory for width and length of each interconnect, and the number of contacts and vias at each node in a circuit, and (2) estimate the overall circuit electromigration failure rate and/or cumulative percent failure as functions of time, temperature, voltage, frequency, and previous stress (e.g., burn-in)

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