ESD failure modes: characteristics mechanisms, and processinfluences
Amerasekera, A.; van den Abeelen, W.; van Roozendaal, L.; Hannemann, M.; Schofield, P.
Electron Devices, IEEE Transactions on
Volume 39, Issue 2, Feb 1992 Page(s):430 - 436
Digital Object Identifier   10.1109/16.121703
Summary:Electrostatic discharge (ESD) failure modes in advanced CMOS processes have been electrically and physically characterized, and an analysis has been made of the mechanisms of each of the main failure modes. The physical failure modes have been related to the electrical degradation and, therefore, the electrical signatures of the damage mechanisms have been obtained. The distribution of the electrical characteristics after ESD stress, for a given process or design variation, can then be used to identify freak failures and process defects. Investigations of the influence of processing steps such as silicides, lightly doped drains (LDDs), thin gate oxides, bird's-beak suppression, and barrier metallization on the electrical damage characteristics and the failure modes are presented and analyzed

» View citation and abstract

Log in by entering your IEEE Web Account Username and Password.

IEEE Communications Society members: If you subscribe to the IEEE Electronic Periodicals Package or IEEE Electronic Periodicals Package Plus, you must access your subscription at www.comsoc.org.

Check with your librarian, information professional, or system manager to determine if you need to log in. Please complete the online Technical Support Form if you need assistance.

Select the Purchase History link to access the document. You will have 5 Days after purchase to access the Full Text PDF. Please complete the online Technical Support Form if you need assistance.

• Search and access Abstract records free of charge
• Register for table of contents alerts
• Purchase Full Text PDF documents

» Learn more about subscription options or how to become an IEEE Member.