An optimization technique for the design of multiple valued PLAapos;s
Asari, K.V.; Eswaran, C.
Computers, IEEE Transactions on
Volume 43, Issue 1, Jan 1994 Page(s):118 - 122
Digital Object Identifier   10.1109/12.250617
Summary:An optimization technique for the design of two types of multiple-valued PLAs is described. In a type-I PLA, the multiple-valued function is realized directly, whereas in a type-II PLA, output encoding is used to encode the binary output of the PLA. In both types, multiple function literal circuits are used for the purpose of minimization. It is shown that the proposed technique leads to a considerably reduced size of PLA when compared to the earlier techniques

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