Rapid layout of a continuous-time transconductance-C filter

Recent results in the design automation of continuous-time transconductance-C filters are presented. These results are limited to grounded capacitors and are reported only for CMOS technologies. A high-level behavioral description of an LC ladder is outlined using a signal-flow graph technique. It is shown that a simple, four-line grammar provides enough versatility for several design generators to produce files for SPICE analysis and Magic layouts of the signal-flow graph simulation of the LC ladder. Areas of future work in these early stages of development of design automation of analog subsystems and circuits are suggested.<
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